A High Dynamic Range Digitally- Controlled Oscillator (DCO) for All-Digital PLL Systems
نویسندگان
چکیده
In this paper, a new high dynamic range DigitallyControlled Oscillator (DCO) for All-DPLL systems is proposed. The proposed DCO is based on using a ΔΣ modulator as a Digital-to-Analog converter. Using ΔΣ DAC can provide a very high resolution (18-bit) control on the DCO. The ΔΣ DAC output is a 2-level pulse signal that needs to be filtered for cancelling the out of band shaped noise. The used ΔΣ modulator is a 4 order MASH ΔΣ modulator working with the OSR of 128 and the sampling frequency of 450MHz. the proposed DCO is used in a PLL to synthesize the frequency in the range of 1700MHz to 1800MHz for GSM-1800 application. The achieved phase noise for this PLL based synthesizer in whole the range is -115 dBc/Hz at the offset frequency of 500 kHz. The designed ADPLL including the DCO is simulated in ADS with 0.18μm CMOS technology.
منابع مشابه
Design of Low Noise 16-bit CMOS Digitally Controlled Oscillator
In this paper, a new differential delay cell is proposed and 16-bit Digital Controlled Oscillator (DCO) based on proposed delay cell is designed. The 16-bit DCO consist of 4-stages differential delay cell in ring structure and a digital control scheme has been used to improved noise characteristics. The structure of the DCO utilizes dual delay path techniques to achieve high oscillation frequen...
متن کاملFast-locking all-digital phase-locked loop with digitally controlled oscillator tuning word estimating and presetting
Design of a fast-locking phase-locked loop (PLL) is one of the major challenges in today’s wireless communications. A recently reported digitally controlled oscillator (DCO)-based all-digital PLL (ADPLL) can achieve an ultrashort settling time of 10 ms. This study describes a new DCO tuning word (OTW) presetting technique for the ADPLL to further reduce its settling time. Estimating the require...
متن کاملLow Jitter ADPLL based Clock Generator for High Speed SoC Applications
An efficient architecture for low jitter All Digital Phase Locked Loop (ADPLL) suitable for high speed SoC applications is presented in this paper. The ADPLL is designed using standard cells and described by Hardware Description Language (HDL). The ADPLL implemented in a 90 nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. ...
متن کاملA Precise ΔΣ-based Digitally Controlled Oscillator (DCO) for All-Digital PLL
A Digitally Controlled Oscillator (DCO) for the frequency band of 1700-1900 MHz is presented. This architecture achieves a frequency resolution less than 1-kHz. The DCO is a part of an All-Digital Phase-Locked Loop (ADPLL) for GSM-1800 and GSM-900 applications implemented in a 0.18 μm CMOS process. In this architecture an 18-bit delta sigma digital to analog converter and a voltage controlled L...
متن کاملA Standard Cell-Based Frequency Synthesizer with Dynamic Frequency Counting
SUMMARY This paper presents a standard cell-based frequency synthesizer with dynamic frequency counting (DFC) for multiplying input reference frequency by N times. The dynamic frequency counting loop uses variable time period to estimate and tune the frequency of digitally-controlled oscillator (DCO) which enhances frequency detection's resolution and loop stability. Two ripple counters serve a...
متن کامل